`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   06:04:57 07/09/2012
// Design Name:   multiplicador
// Module Name:   C:/Documents and Settings/prueba/tb_mult.v
// Project Name:  prueba
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: multiplicador
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_multiplicador # (parameter N=16)();
    reg G, reset, clk;
    reg [N-1:0] bus_in;
    wire [2*N-1:0] out;
    
    multiplicador dut(G, reset, clk, bus_in, out);
    always
    begin
        clk=1; #5; clk=0; #5;
    end

    initial begin
        reset=1;G=0;#11;reset=0;bus_in=14;G=1;#20;G=0;#10;bus_in=24;G=1;#10;G=0;#10;#10;#10;#100;#1;#100;
        reset=1;G=0;#11;reset=0;bus_in=53;G=1;#20;G=0;#10;bus_in=137;G=1;#10;G=0;#10;#10;#10;#100;#1;#100;
        reset=1;G=0;#11;reset=0;bus_in=42157;G=1;#20;G=0;#10;bus_in=38548;G=1;#10;G=0;#10;#10;#10;#100;#1;#100;
    end
endmodule